It is known that device performance can be improved by adding compressive stress to PMOS devices and tensile stress to NMOS devices. For example, embedded epitaxial SiGe in PMOS source/drain (S/D) regions has become mainstream for PMOS devices in CMOS technology since its implementation around the 90 nm node. Embedded epitaxial SiC in NMOS source/drain (S/D) regions also became mainstream for NMOS devices at around the 45 nm node.
Regarding compressively stressed PMOS devices, the conventional process to incorporate epitaxial S/D compressive stress inducing species (e.g., SiGe) for PMOS devices in CMOS flows usually involves patterning and selective dry etch of the PMOS S/D regions. The extra pattern step is to allow selective substrate (e.g., silicon) etch of the PMOS S/D regions which results in additional cycle time and manufacturing cost. In addition, because the final PMOS transistor performance depends on the shape of the substrate recess formed, plasma dry etch has difficulty in controlling that shape due to lithographic effects such as gate electrode (e.g., polysilicon) pitch dependence and the proximity effect. To form tensile stressed NMOS devices, conventional processing analogous to the above-described processing for forming compressively stressed PMOS devices is generally used. Accordingly, there is a need for new methods to fabricate CMOS integrated circuits (ICs) having compressive stressed PMOS devices and/or tensile stressed NMOS devices, and for CMOS ICs fabricated therefrom.